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(R)
NO
October 2000
CT T O DU M EN E P R P LA C E T O LE RE O B S EN D ED OM M RE C
HSP50307
Burst QPSK Modulator
Features
* 256 KBPS Data Rate and 128 KBPS Baud Rate * Burst QPSK Modulation * Programmable Carrier Frequency from 8MHz to 15MHz With a Frequency Step Size of 32kHz * = 0.5 Root Raised Cosine (RRC) Filtering For Spectrum Shaping * On-Board Synthesizer * Programmable Output Level From 22 to 62dBmV in 1dB Steps * Programmable Charge Pump Current Control * 62dBmV Differential Output Driver for 75 Cable
Description
The HSP50307 is a mixed signal burst QPSK Modulator for upstream CATV Applications. The HSP50307 demultiplexes and modulates a serial data stream onto an RF Carrier centered between 8 and 15MHz. The signal spectrum is shaped with = 0.5 root raised cosine (RRC) digital filters. On-chip filtering limits spurs and harmonics to levels below -35dBc during transmissions. The output power level is adjustable over a 40dB range in 1dB steps. The maximum differential output level is +62dBmV into 75. A transmitter inhibit function disables the RF output outside the burst interval. The differential output amplifier int7-erfaces to the cable via a transformer. The Block Diagram of the HSP50307 QPSK Modulator is shown below. The HSP50307 consists of a digital control interface, an I/Q generator, a synthesizer, and a quadrature modulator. The data clock is derived from the master clock. The HSP50307 demultiplexes the input data bits into in-phase (I) and quadrature (Q) data streams. The first bit and subsequent alternating bits of the burst are in-phase data. The two data streams are filtered, converted from digital to analog, and low pass filtered to produce the baseband I and Q analog signals.
PKG. NO. M28.3
Applications
* Burst QPSK Modulator * HSP50307EVAL1 Evaluation Board Is Available
Ordering Information
PART NUMBER HSP50307SC TEMP. RANGE (oC) 0 to 70 PACKAGE 28 Ld SOIC
The baseband signals are up-converted to RF in the Quadrature Modulation Section. The synthesizer provides the local oscillator (LO) for the quadrature modulator. The frequency is programmable via the control interface with a resolution of 32kHz. The output of the quadrature modulator is low pass filtered to remove harmonic distortion.
Block Diagram
RCLK VCO_IN VCO_SET PD_OUT RESET CCLK C_EN CDATA TX_EN I TX_DATA DEMUX CONTROL INTERFACE SYNTHESIZER
QUAD GEN
QUADRATURE MODULATOR
I/Q GENERATOR 8RRC 9 D/A LPF
MOD_OUT+ LPF PGA MOD_OUT+ D/A LPF TX_EN
Q
9 8RRC
TXCLK MCLK /100
QBBOUT
IBBOUT
Indicates analog circuitry.
MCLK MUST ALWAYS BE PRESENT FOR PROPER OPERATION
QBBIN
IBBIN
DAC_REF
VCM_REF
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved 1
FN4219.1
HSP50307 Pinout
28 LEAD SOIC TOP VIEW
MCLK 1 TXCLK 2 TX_EN 3 TX_DATA 4 RESET 5 DGND 6 AVCC 7 AGND 8 IBBOUT 9 QBBOUT 10 QBBIN 11 IBBIN 12 DAC_REF 13 VCM_REF 14 28 CCLK 27 CDATA 26 C_EN 25 DVCC 24 RCLK 23 AGND 22 PD_OUT 21 VCO_IN 20 VCO_SET 19 AVCC 18 MOD_OUT17 MOD_OUT+ 16 AVDD 15 AGND
Pin Description
SYMBOL MCLK TXCLK TX_EN TX_DATA RESET TYPE I O I I I Master clock input (25.6MHz). (D) PSK data clock (256kHz) for PSK_DATA_IN. (D) Transmit Enable. When high, the modulator output is enabled. This pin should be high for the entire burst. The signal is extended internally until data has fully exited the part before turning off for spurious free turn on and turn off. (D) 256 KBPS serial data input. (D) Digital Reset Pin (active low). The part is reset immediately on assertion of the reset pin. The output of the part is disabled on the assertion of reset. The part will come out of reset 2 master clock periods after the reset is deasserted. Reprogramming (see Control Interface Section) is needed after deassertion of reset for proper operation. (D) Negative supply for the digital filters and control. (P) Positive supply for the quadrature modulator. AVCC should be tied to +5V analog. (P) Negative supply for the quadrature modulator. AGND is tied to GND. (P) I baseband filtered output. (A) Q baseband filtered output. (A) Q baseband modulator input. (A) I baseband modulator input. (A) D/A reference node. A 0.1F capacitor to ground is suggested. (A) Modulator common mode reference node. A 0.1F capacitor to ground is suggested. (A) Negative supply for the cable interface. (P) Positive supply for the cable interface (+9V analog). (P) Positive output drive pin for the cable interface. (A) Negative output drive pin for the cable interface. (A) DESCRIPTION
DGND AVCC AGND IBBOUT QBBOUT QBBIN IBBIN DAC_REF VCM_REF AGND AVDD MOD_OUT+ MOD_OUT-
I I I O O I I O O I I O O
2
HSP50307 Pin Description
SYMBOL AVCC VCO_SET VCO_IN PD_OUT AGND RCLK DVCC C_EN CDATA CCLK TYPE I I/O I O I I I I I I (Continued) DESCRIPTION Positive supply for the synthesizer (+5V analog). (P) VCO free running frequency set resistor (normally 6.25k). (D) Voltage-controlled oscillator control voltage. (D) Phase/frequency detector output. (D) Negative supply for the synthesizer. (P) Synthesizer reference clock input (2.048MHz). (D) Positive supply for the digital filters and control (+5V digital). (P) Control interface enable for 3 wire interface. See Control Interface Section. (D) Serial data input for 3 wire interface. See Control Interface Section. (D) 3 wire interface clock. See Control Interface Section. (D)
NOTE: (A) = analog, (D) = digital, (P) = power.
Functional Description
The HSP50307 is designed to transmit 256 KBPS data using QPSK modulation on a programmable carrier over 75 cable lines. The incoming 256 KBPS data is first demultiplexed into in-phase (I) and quadrature (Q) data streams. The burst QPSK modulator shapes the two 128 KBPS demultiplexed data streams using interpolateby-8 root-raised cosine (RRC) filters with = 0.5. The resulting 1.024MHz data streams are sent through D/A converters and are then sent through low-pass reconstruction filters for over 40dB image rejection. The baseband analog output and input pins allow the signals to be AC coupled. The returning analog signal is upconverted by an analog quadrature modulator. The control section is configured by loading 23 bits of information via a three-wire interface. These bits configure the DSP filter section, the carrier frequency, the analog synthesizer, and the output driver sections.
0.8 0.7 0.6 COEFFICIENT VALUE 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 1 8 16 24 32 40 TAP NUMBER 48 56 64
FIGURE 1. NORMALIZED IMPULSE RESPONSE OF THE RRC INTERPOLATION FILTER WITH = 0.5
MKR 8.0960MHz -16.83dBm
Digital Filters
The burst QPSK modulator uses an interpolate-by-8 digital RRC filter on both the I and Q data streams. The shaping factor is set to = 0.5. The FIR order of the digital RRC filter is 64. Figure 1 shows the impulse response of the RRC filter. Figure 2 is a spectrum analyzer plot of the modulator output for a baud rate of 128 kbaud and a pseudorandom data pattern. The 128kHz 3dB bandwidth and 192kHz stopband edges are readily apparent.
PEAK LOG 5dB/
REF -15.0 dBm
# AT 60dB
WA SB SC FS CORR
CENTER 8.0960MHz #RES BW 300Hz
VBW 300Hz
SPAN 400.0kHz SWP 13.3s
FIGURE 2. SPECTRUM OF 8.096MHz RANDOM DATA MODULATED CARRIER
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HSP50307 Control Interface
The QPSK modulator is configured via a serial three wire interface. When C_EN is high, 23 bits are shifted in at the CDATA pin on the falling edge of CCLK. Figure 3 shows the timing diagram for loading the serial configuration data. Table 1 describes the 23-bit serial configuration data. See the Synthesizer Section for more details on the frequency control bits.
TABLE 1. 23-BIT SERIAL DATA CONTROL INTERFACE DESCRIPTION BIT POSITION D0-D2 (Note) D3-D9 D10 FUNCTION Synthesizer Control Bits Synthesizer Control Bits Synthesizer Enable DESCRIPTION Pre-scaler control register. A = (0 to 5), D2 is the MSB. Feedback Counter Control Register. M = (41 to 103) D9 is the MSB. Active high. This bit activates chip bias networks for normal operation. D10 = 0 places part in low power mode.
Synthesizer
The synthesizer generates the quadrature LO's for modulating the baseband data to RF. The carrier frequency is phase locked to the reference clock (RCLK). The carrier frequency, FC, has a frequency range of 8MHz to 15MHz with a resolution of 32kHz. Equation 1 gives the relationship between FC and the frequency of RCLK and the frequency control bits, M and A.
6(M + 1) + A F C = -------------------------------- FREF , 64 (EQ. 1)
where FREF equals the frequency of RCLK. Also, M and A can be determined by
64 A M + --- = ----6 6 FC -------------- - 1. F REF (EQ. 2)
"A" ranges from 0 to 5 and "M" ranges from 41 to 103. A and M are programmed via control bits D0-D2 and D3-D9, respectively. Values outside these ranges are invalid.
D11
Charge Pump D11 = 0 sets charge pump current to 500A. Current D11 = 1 sets charge pump current to Control 1mA. Three-State Control D12 = 0 three-states the charge pump output when a pump up and down command occur simultaneously. D12 = 1 disables three-state. Controls output power level. The binary value of the register corresponds to an attenuation amount. For example, 000100 corresponds to 4dB attenuation from the maximum 62dBmV level. D18 is the MSB. Used for test/diagnostic purposes. Set to 000. Test mode; D22 = 0 sets the burst QPSK modulator in normal mode. D22 = 1 disables the digital filter.
I/Q Generator
The I/Q Generator Section demultiplexes and time aligns the 256 KBPS input data into two data streams, I and Q. The first data bit following the assertion of the TX_EN signal is the I data of the first I/Q pair. Each I/Q pair determines the phase angle of the QPSK transmission signal. The relationship between I/Q pairs and phase angles is shown in Table 2. Since the QPSK encoding requires a pair of I and Q information to transmit one symbol, an even number of data bits must be provided for each burst.
TABLE 2. QPSK ENCODING I 0 0 1 1 Q 0 1 0 1 PHASE 45o 135o -45o -135o
D12
D13-D18
Attenuation Control
D19-D21 D22
Reserved DSP Shut Down
NOTE: D0 is the first bit shifted into the part.
4
HSP50307
tCCH
CCLK tCDS C_DATA D22 D21 D20 tCDH D19 D3 D2 D1 D0
C_EN
FIGURE 3. CONTROL INTERFACE TIMING DIAGRAM
5
HSP50307 Applications Example
+5VDIGITAL
25.6MHz OSC
0.1F DGND
1 2 DATA SOURCE 3 4 +5VANALOG 5 6 DGND 0.1F 9 10 11 0.1F 12 0.1F 13 0.1F 14 0.1F 7 8
MCLK TXCLK TX_EN TX_DATA RESET DGND AVCC AGND IBBOUT QBBOUT QBBIN IBBIN DAC_REF VCM_REF
CCLK 28 CDATA 27 C_EN 26 DVCC 25 RCLK 24 AGND 23 2k PD_OUT 22 100pF VCO_IN 21 6.25k VCO_SET 20 AVCC 19 MOD_OUT- 18 MOD_OUT+ 17 0.01F
CONTROL PROC.
2.048MHz OSC
+5VANALOG 0.01F
37.5 0.1F
CABLE TRANSFORMER RFOUT
37.5 0.1F AVDD 16 AGND 15 0.1F +9VANALOG
AGND
AGND
FIGURE 4. APPLICATIONS EXAMPLE OF THE HSP50307
Figure 4 shows an applications example of the HSP50307. The MCLK source operates at 25.6MHz, and the RCLK operates at 2.048MHz. 0.1F capacitors are connected from the IBBOUT to IBBIN and the QBBOUT to QBBIN, providing AC coupling to the Analog Upconverter Section of the HSP50307. The control processor sends the 23-bit control word via the three-wire interface. The data source receives the 256kHz TXCLK from the HSP50307 and transmits data and enable signal at the 256kHz rate. The DAC_REF and VCM_REF are connected to 0.1F capacitors to ground. Each of the differential drivers are loaded with a 37.5 resistor and a 0.1F capacitor. The 37.5 resistors provide matching to the 75 cable. The capacitors perform AC coupling. The drive paths are sent to the cable transformer for data transmissions.
Table 3 shows the general functional specifications for the applications example shown in Figure 4. It gives an overview of what is being accomplished but does not specify an exact carrier frequency or other programmable functions. These specifications are met given a valid control word combination and the applications circuit shown in Figure 4. Table 4 summarizes the performance of the applications example shown in Figure 4. Again, these specifications are met given a valid programmed mode. NOTE: The HSP50307 is sensitive to layout. Users must make sure the input signals do not couple back into the output signals. The performance of the HSP50307 is also sensitive to the decoupling capacitors between 1) QBBOUT and QBBIN and 2) IBBOUT and IBBIN. The values shown in Figure 4 are recommended.
6
HSP50307
TABLE 3. GENERAL FUNCTIONAL SPECIFICATIONS AVCC, DVCC = +5V, AVDD = +9V; RCLK = 2.048MHz; MCLK = 25.6MHz; TA = 0oC to 70oC PARAMETER QPSK Carrier Frequency QPSK Carrier Frequency Step Size Modulation Bandwidth Raised Cosine Filter Response Excess Bandwidth () Transmit Level Adjust Data Rate Baud Rate NOTE: May operate up to 20MHz. MIN 8.0 TYP 32 192 0.5 40 256 128 MAX 15 (Note) UNIT MHz kHz kHz dB KBPS KBPS
TABLE 4. QPSK PERFORMANCE SPECIFICATIONS AVCC, DVCC = +5V, AVDD = +9V; RCLK = 2.048MHz; MCLK = 25.6MHz; TA = 0oC to 70oC PARAMETER Output Spurious Signals Less Than 54MHz Output Spurious Signals Greater Than 54MHz Off Mode Spurs Transmit Level (D18-D13 = 000000) Output Gain Adjust Relative Accuracy Absolute Output Accuracy at Any Step QPSK Carrier Phase Noise at 10kHz Offset QPSK Carrier Phase Noise at 1kHz Offset QPSK Modulator Carrier Suppression QPSK I/Q Amplitude Imbalance QPSK I/Q Phase Imbalance QPSK Passband Amplitude Ripple MIN 59 -0.5 -3.0 35 -0.3 TYP -40 -60 62 0.2 2 40 MAX -35 -50 -30 65 0.5 3.0 -75 -60 0.5 2.0 0.3 UNITS dBc dBc dBmV dBmV dB dB dBc/Hz dBc/Hz dBc dB Degree dB
7
HSP50307
Absolute Maximum Ratings
5V Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.0V 9V Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.0V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1, HBM
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to 70oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
PARAMETER 5V Supply Voltage 9V Supply Voltage 5V Supply Current 9V Supply Current Logical One Input Voltage Logical Zero Input Voltage Output High Voltage Output Low Voltage
RCLK = 2.048MHz; MCLK = 25.6MHz; TA = 0oC to 70oC SYMBOL/PIN AVCC, DVCC AVDD IAVCC, IDVCC IAVDD VIH VIL VOH VOL MIN 4.75 8.55 3.325 2.6 TYP 5.0 9.0 55 60 MAX 5.25 9.45 1.575 0.4 UNIT V V mADC mADC V V V V
AC Electrical Specifications
PARAMETER RESET Pulse Width MCLK Period (25.6MHz) RCLK Period (2.048MHz) RCLK High RCLK Low CCLK Period (5MHz) CCLK High CCLK Low CDATA Setup to CCLK CDATA Hold from CCLK C_EN Strobe Edge to CCLK TXCLK Period (256kHz) TXCLK High TXCLK Low TX_DATA Setup to TXCLK TX_DATA Hold from TXCLK
AVCC, DVCC = +5V, AVDD = +9V; RCLK = 2.048MHz; MCLK = 25.6MHz; TA = 0oC to 70oC SYMBOL tRES tMCP tRCP tRCH tRCL tCCP tCCH tCCL tCDS tCDH tCES tDCP tDCH tDCL tDIS tDIH MIN 500 98 98 200 150 150 50 -100 195 195 150 0 TYP 39.1 488 3910 MAX 50 100 UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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HSP50307 Waveforms
tMCP
1 MCLK
2 tRCP PART IS ACTIVE AGAIN tRCH tRCL
tRES RESET RCLK
FIGURE 5. RESET AND MCLK WAVEFORMS
FIGURE 6. RCLK WAVEFORM
tCCP tCCL CCLK tCDS CDATA TXCLK tDIS C_EN tCES TX_DATA tDIH tCDH tDCL tDCP tDCH tCCH
FIGURE 7. CONFIGURATION WAVEFORMS
FIGURE 8. TRANSMIT DATA WAVEFORMS
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